Abstract:

This paper introduces the design of a convolutional neural network (CNN) in-memory computing accelerator neuron array, which integrates an SRAM storage architecture with charge-domain computation. In this design, weights are stored directly in 6T SRAM cells, and multiplication is implemented using XNOR logic. The resulting bit-wise products are converted into charge on integrated capacitors, which share and accumulate charges proportional to their corresponding weights. This approach creates a highly scalable analogue in-memory computing architecture that addresses the “memory-wall” bottleneck and mitigates the energy inefficiencies of traditional von Neumann systems. Tailored for edge-computing applications—such as virtual-reality and augmented-reality headsets, as well as autonomous electric vehicles—this neuron array accelerator significantly enhances the speed of image-processing algorithms while adhering to strict power constraints.

As AI algorithms and edge devices become increasingly prevalent, concerns about power consumption and environmental impact have gained prominence. While GPUs and TPUs offer impressive raw performance, their dependence on off-chip memory exacerbates the memory-wall issue, and their high power consumption and cooling demands hinder sustainable operation. Energy efficiency has therefore become a critical challenge for next-generation AI hardware. In contrast, our analogue in-memory computing solution delivers superior bandwidth and computational speed while substantially reducing energy consumption. This aligns with green computing principles and enables battery-powered or even solar-driven, self-sustaining operation in remote or mobile environments. Additionally, compared to current-domain in-memory computing approaches, the charge-domain technique offers more linear multiply-accumulate (MAC) results, enhancing accuracy and simplifying downstream signal processing.

Our accelerator operates at a 1.8 V supply, producing output voltages ranging from 0 to 1.8 V in 180 nm TSMC process. By precisely sizing capacitor ratios based on stored weights, the neuron array completes multi-bit MAC operations in just two clock cycles. Energy per MAC is reduced to approximately 0.175 pJ, achieving an overall efficiency of 5.73 TOPS/W. The analogue outputs of the neuron matrix can be digitized using a minimum 7-bit analogue-to-digital converter (ADC). The architecture supports direct computation on digital input/output streams and, with minor modifications, can process raw analogue signals from image sensors. The proposed design has been thoroughly validated through circuit-level simulations, confirming its suitability for accelerating all convolutional layers in modern CNNs.